Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology have greatly increased demand for high speed under various modes of operation of these SDRAM circuits. These same advances, however, also demand minimal power consumption for laptop computers and other battery powered applications. SDRAM circuits frequently produce data in 4-bit, 8-bit and full-page serial and interleaved burst modes at high system clock frequencies. At these high clock frequencies of extended duration, burst cycle current (ICC4) is a critical component of active power. Previous SDRAM designs have had significant ICC4 current due to propagation of column address signals throughout the SDRAM column decode path with each column address transition. This technique provided high-speed data access at the cost of multiple column decode path transitions and significant ICC4 power consumption for each burst cycle. For example, a local column factor circuit of the prior art (FIG. 6) was used to generate local column factor address signals CFnuv from global column factor signal CFuv and bank address signal BANKn, where n, u and v are integer variables. Each time a bank was unselected, however, all local column factor signals CFnuv were taken low. When the bank was reselected for a subsequent access, local column factor signals CFnuv were often returned to their previous logic state, resulting in needless transitions of local column factor signals. These column factor signals propagated through highly capacitive bus lines in the column decode portion of each array, thereby increasing burst cycle current ICC4.